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?2008 scillc. all rights reserved. publication order number: july 2008 - rev. 9 N25S818HA/d N25S818HA 256kb low power serial srams 32k 8 bit organization overview the on semiconductor serial sram family includes several integrated memory devices including this 256kb serially accessed static random access memory, internally organized as 32k words by 8 bits. the devices are designed and fabricated using on semiconductor?s advanced cmos technology to provide both high-speed performance and low power. the devices operate with a single chip select (cs ) input and use a simple serial peripheral in terface (spi) serial bus. a single data in and data out line is used along with a clock to access data wit hin the devices. the N25S818HA devices include a hold pin that allows communication to the device to be paused. while paused, input transitions will be ignored. the devices can operate over a wide temperature range of -40 o c to +85 o c and can be available in several standard package offerings. features ? power supply range 1.7 to 1.95v ? very low standby current typical isb as low as 200na ? very low operating current as low as 3ma ? simple memory control single chip select (cs ) serial input (si) and serial output (so) ? flexible operating modes word read and write page mode (32 word page) burst mode (full array) ? organization 32k x 8 bit ? self timed write cycles ? built-in write protection (cs high) ?hold pin for pausing communication ? high reliability unlimited write cycles ? rohs compliant packages green soic and tssop device options part number density power supply (v) speed (mhz) package typical standby current read/write operating current N25S818HAs2 256kb 1.8 16 soic 200na 3 ma @ 1mhz N25S818HAt2 tssop
rev. 9 | page 2 of 15 | www.onsemi.com n25s0818ha functional block diagram pin names pin name pin function cs chip select input sck serial clock input si serial data input so serial data output hold hold input nc no connect v cc power v ss ground 1 cs soic 2 3 4 8 5 7 6 so nc vss vcc hold sck si 1 cs tssop 2 3 4 8 5 7 6 so nc vss vcc hold sck si package configurations sram array decode logic cs clock circuitry sck data in receiver si data out buffer so hold
rev. 9 | page 3 of 15 | www.onsemi.com n25s0818ha absolute maximum ratings 1 item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.5 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -40 to +85 o c soldering temperature and time t solder 260 o c, 10sec o c 1. stresses greater than those listed above may cause permanent da mage to the device. this is a stress rating only and functiona l operation of the device at these or any ot her conditions above thos e indicated in the operating se ction of this specification i s not implied. exposure to absolute maximum rating condi tions for extended periods may affect reliability. operating characteristics (ove r specified temperature range) item symbol test conditions min. typ 1 1. typical values are measured at vcc=vcc typ., t a =25c and are not 100% tested. max unit supply voltage v cc 1.8v device 1.7 1.95 v input high voltage v ih 0.7 x v cc v cc +0.3 v input low voltage v il ?0.3 0.8 v output high voltage v oh i oh = -0.4ma v cc ?0.5 v output low voltage v ol i ol = 1ma 0.2 v input leakage current i li cs = v cc , v in = 0 to v cc 0.5 a output leakage current i lo cs = v cc , v out = 0 to v cc 0.5 a read/write operating current i cc1 f = 1mhz, i out = 0 3ma i cc2 f = 10mhz, i out = 0 6ma i cc3 f = fclk max, i out = 0 10 ma standby current i sb cs = v cc , v in = v ss or v cc 200 500 na capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 7pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 7pf
rev. 9 | page 4 of 15 | www.onsemi.com n25s0818ha timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc output load cl = 100pf operating temperature -40 to +85 o c timing item symbol min. max. units clock frequency f clk 16 mhz clock rise time t r 2 us clock fall time t f 2us clock high time t hi 32 ns clock low time t lo 32 ns clock delay time t cld 32 ns cs setup time t css 32 ns cs hold time t csh 50 ns cs disable time t csd 32 ns sck to cs t scs 5ns data setup time t su 10 ns data hold time t hd 10 ns output valid from clock low t v 32 ns output hold time t ho 0ns output disable time t dis 20 ns hold setup time t hs 10 ns hold hold time t hh 10 ns hold low to output high-z t hz 10 ns hold high to output valid t hv 50 ns
rev. 9 | page 5 of 15 | www.onsemi.com n25s0818ha serial input timing serial output timing hold timing cs t css msb in sck so si lsb in t f t r t cld t csh t csd t su t hd high-z t scs cs t lo msb out sck si so lsb out t dis t csh t hi t v don?t care cs t hs n+2 sck si so t su t hz t hh n+1 n high-z t hs t hh t hv nn-1 nn-1 n+2 n+1 n hold don?t care
rev. 9 | page 6 of 15 | www.onsemi.com n25s0818ha functional operation basic operation the 256kb serial sram is designed to interface direct ly with a standard serial peripheral interface (spi) common on many standard micro-controllers. it may also interface with other non-spi ports by programming discrete i/o lines to operate the device. the serial sram contains an 8-bit instruction register and is accessed via the si pin. the cs pin must be low and the hold pin must be high for the entire operation. data is sampled on the first rising edge of sck after cs goes low. if the clock line is shared, the user can assert the hold input and place the device into a hold mode. after releasing the hold pin, the operation will resume from the point where it was held. the following table contains the possible instructions an d formats. all instructions, addresses and data are transferred msb first and lsb last. control signal descriptions signal name i/o description cs chip select i a low level selects the device and a high level puts the device in standby mode. if cs is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. when cs is high, so is in high-z. cs must be driven low after power-up prior to any sequence being started. sck serial clock i synchronizes all activities between the memory and controller. all incoming addresses, data and instructions are latched on the rising edge of sck. data out is updated on so after the falling edge of sck. si serial data in i receives instructions, addresses and data on the rising edge of sck. so serial data out o data is transferred out after the falling edge of sck. hold hold i a high level is required for normal operation. once the device is selected and a serial sequence is started, this input may be taken low to pause serial communica- tion without resetting the serial sequence. the pin must be brought low while sck is low for immediate use. if sck is not low, the hold function will not be invoked until the next sck high to low transition. the device must remain selected during this sequence. so is high-z during the hold time and si and sck are inputs are ignored. to resume operations, hold must be pulled high while the sck pin is low. lowering the hold input at any time will take to so output to high-z. instruction set instruction instruction format description read 0000 0011 read data from memory starting at selected address write 0000 0010 write data to memory starting at selected address rdsr 0000 0101 read status register wrsr 0000 0001 write status register
rev. 9 | page 7 of 15 | www.onsemi.com n25s0818ha read operations the serial sram read is selected by enabling cs low. first, the 8-bit read instruction is transmitted to the device followed by the 16-bit address with the msb being a don?t care. after the read instruction and addresses are sent, the data stored at that address in memory is shifted out on the so pin after the output valid time from the clock edge. if operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequent ially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. this can be continued for the entire page leng th of 32 words long. at the end of the page, the addresses pointer will be wr apped to the 0 wo rd address within the page and the operation can be continuously looped over the 32 words of the same page. if operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to pr ovide clock pulses. the in ternal address pointer is automatically incremented to the next higher address af ter each word of data is read out. this can be continued for the entire array and when the highes t address is reached (7fffh), the address counter wraps to the address 0000h. this allows the burst read cycle to be continued indefinitely. all read operations are terminated by pulling cs high. word read sequence cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 210 7 6543 210 high-z 16-bit address data out so 21 23 22 24 28 29 30 31 26 27 25 000 0 0 011
rev. 9 | page 8 of 15 | www.onsemi.com n25s0818ha page and burst read sequence page read sequence burst read sequence cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 210 7 6543 210 high-z 16-bit address data out from addr 1 so 21 23 22 24 28 29 30 31 26 27 25 000 0 0 011 7 6543 210 data out from addr 2 7 6543 210 7 6543 210 ... 32 34 33 35 39 40 41 42 37 38 36 43 45 44 46 47 don?t care don?t care addr 1 data out from addr 3 data out from addr n page x word y page x word y+2 page x word y+1 page x word 31 page x word 0 page x word 1 si so data words: sequential, at the end of the page the address wraps back to the beginning of the page 16-bit address page address (x) word address (y) page x word y page x word 31 page x word y+1 page x word 0 page x+1 word y page x+1 word y+1 si so 16-bit address page address (x) word address (y) data words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. at that time, the address increments to the next page and the burst continues. . . . page x word 1 . . . page x word y-1
rev. 9 | page 9 of 15 | www.onsemi.com n25s0818ha write operations the serial sram write is selected by enabling cs low. first, the 8-bit write instruction is transmitted to the device followed by the 16-bit address with the msb being a don?t care. after the write instruction and addresses are sent, the data to be stored in memory is shifted in on the si pin. if operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is se quential on the same page. simply write the data on si pin and continue to provide clock pulses. the internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. this can be continued for the entire page length of 32 words long. at the end of the page, the addresses po inter will be wrapped to the 0 word address within the page and the operation can be cont inuously looped over the 32 words of the same page. the new data will replace data alread y stored in the memory locations. if operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. the internal address pointer is automatically incremented to the ne xt higher address after each word of data is read out. this can be continued for the entire array and when the highes t address is reached (7fffh), the address counter wraps to the address 0000h. this allows the burst writ e cycle to be continued indefinitely. again, the new data will replace data already st ored in the memory locations. all write operations are terminated by pulling cs high. word write sequence cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 2107 6543 210 high-z 16-bit address data in so 21 23 22 24 28 29 30 31 26 27 25 000 0 0 010 ...
rev. 9 | page 10 of 15 | www.onsemi.com n25s0818ha page and burst write sequence page write sequence burst write sequence cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 2107 6543 210 high-z 16-bit address data in to addr 1 so 21 23 22 24 28 29 30 31 26 27 25 000 0 0 010 7 6543 210 data in to addr 2 7 6543 210 7 6543 210 ... 32 34 33 35 39 40 41 42 37 38 36 43 45 44 46 47 addr 1 data in to addr 3 data in to addr n high-z 16-bit address page address (x) word address (y) page x word y page x word y+2 page x word y+1 page x word 31 page x word 0 page x word 1 si so data words: sequential, at the end of the page the address wraps back to the beginning of the page high-z page x word y page x word 31 page x word y+1 page x word 0 page x+1 word y page x+1 word y+1 si so 16-bit address page address (x) word address (y) data words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. at that time, the address increments to the next page and the burst continues. . . . page x word 1 . . . page x word y-1 high-z
rev. 9 | page 11 of 15 | www.onsemi.com n25s0818ha write status register instruction (wrsr) this instruction provi des the ability to write the status register and select among severa l operating modes. several of the register bits must be set to a low ?0? if any of the other bits are written. the timing sequence to write to the status register is shown below, followed by the organization of the status register. write status register sequence status register cs instruction si 04 3 25 169 810 711 sck 7 6543 210 high-z status register data in so 00 0 00 1 0 12 13 14 15 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 hold function 0 = hold (default) 1 = no hold reserved must = 0 reserved must = 0 mode 0 0 = word mode (default) 1 0 = page mode 0 1 = burst mode 1 1 = reserved
rev. 9 | page 12 of 15 | www.onsemi.com n25s0818ha read status register instruction (rdsr) this instruction provides t he ability to read the status register. the register may be read at any time by performing the following timing sequence. read status register instruction (rdsr) power-up state the serial sram enters a know state at power-up time . the device is in low-power standby state with cs = 1. a low level on cs is required to enter a active state. cs instruction si 04 3 25 169 810 711 sck 7 6543 210 high-z status register data out so 00 0 00 1 0 12 13 14 15 1
rev. 9 | page 13 of 15 | www.onsemi.com n25s0818ha 8-lead plastic small outline, 150mil soic note: 1. all dimensions in millimeters 2. package dimensions exclude mold flash and protusions. parameter sym min nom max pin pitch p 1.27 overall height a 1.35 1.55 1.75 molded package thickness a2 1.32 1.42 1.55 standoff a1 0.10 0.18 0.25 overall width e 5.79 6.02 6.20 molded package width e1 3.71 3.91 3.99 overall length d 4.80 4.90 5.00 chamfer distance h 0.25 0.38 0.51 foot length l 0.48 0.62 0.76 foot angle 048 lead thickness c 0.20 0.23 0.25 lead width b 0.33 0.42 0.51 mold draft angle top 01215 mold draft angle bottom 01215 e1 d p b a2 a1 a 45 o c l h e
rev. 9 | page 14 of 15 | www.onsemi.com n25s0818ha 8-lead plastic thin shrink sm all outline, 4.4 mm tssop note: 1. all dimensions in millimeters 2. package dimensions exclude mold flash and protusions. parameter sym min nom max pin pitch p 0.65 overall height a 1.10 molded package thickness a2 0.85 0.90 0.95 standoff a1 0.05 0.10 0.15 overall width e 6.25 6.38 6.50 molded package width e1 4.30 4.40 4.50 overall length d 2.90 3.00 3.10 foot length l 0.50 0.60 0.70 foot angle 048 lead thickness c 0.09 0.15 0.20 lead width b 0.19 0.25 0.30 mold draft angle top 0510 mold draft angle bottom 0510 e1 d p b a2 a1 a c l e
rev. 9 | page 15 of 15 | www.onsemi.com n25s0818ha ordering information part number power supply package shipping method N25S818HAs21i 1.8v 8-pin soic (rohs compliant) tray N25S818HAt21i 1.8v 8-pin tssop (rohs compliant) tray N25S818HAs21it 1.8v 8-pin soic (rohs compliant) tape & reel N25S818HAt21it 1.8v 8-pin tssop (rohs compliant) tape & reel revision history revision # date change description a october 2005 initial advance release b january 2006 separated density, removed writ e protection and added page and burst modes c january 2006 changed packages to green type d january 2006 changed tssop pinout to match soic e september 2006 split x8 and x16 devices converted to ami semiconductor f may 2007 updated dc parameters g october 2007 maximum frequency changed to 16mhz for 1.8v device h january 2008 removed advance from datasheet changed amis address 9 july 2008 converted to on semiconductor and new part numbers publication orderi ng information literature fulfillment: literature distribution center for on semiconductor po box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east & africa technical support: phone 421-33-790-2910 japan customer focus center: phone 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer a pplication by customer's technical experts. scillc does not convey any license under its patent righ ts nor the rights of others. scillc products are not designe d, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, o r for any other application in which the failure of the scillc product could create a situation where personal inju ry or death may occur. should buyer purchase or use scillc p roducts for any such unintended or unauthorized application, buyer shall indemnify and hold scillc a nd its officers, employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or dea th associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative a ction employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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